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cy7c008v/009v cy7c018v/019v 3.3 v 64 k/128 k 8/9 dual-port static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-06044 rev. *e revised november 9, 2010 3.3 v 64 k/128 k 8/9 dual-port static ram features true dual-ported memory cells which allow simultaneous access of the same memory location 64 k 8 organization (cy7c008) 128 k 8 organization (cy7c009) 64 k 9 organization (cy7c018) 128 k 9 organization (cy7c019) 0.35-micron cmos for optimum speed/power high-speed access: 15/20/25 ns low operating power ? active: i cc = 115 ma (typical) ? standby: i sb3 = 10 ? a (typical) fully asynchronous operation automatic power-down expandable data bus to 16/18 bits or more using master/slave chip select when using more than one device on-chip arbitration logic semaphores included to permit software handshaking between ports int flag for port-to- port communication dual chip enables pin select for master or slave commercial and industrial temperature ranges available in 100-pin tqfp pb-free packages available i/o control address decode a 0l ?a 15/16l ce l oe l r/w l busy l i/o control interrupt semaphore arbitration sem l int l m/s logic block diagram a 0l ?a 15/16l true dual-ported ram array a 0r ?a 15/16r ce r oe r r/w r busy r sem r int r address decode a 0r ?a 15/16r [1] [1] [2] [2] [3] [3] [2] [2] r/w l ce 0l ce 1l oe l i/o 0l ?i/o 7/8l ce l r/w r ce 0r ce 1r oe r i/o 0r ?i/o 7/8r ce r 16/17 8/9 16/17 8/9 16/17 16/17 notes 1. i/o 0 ?i/o 7 for 8 devices; i/o 0 ?i/o 8 for 9 devices. 2. a 0 ?a 15 for 64 k devices; a 0 ?a 16 for 128 k. 3. busy is an output in master mode and an input in slave mode. cy7c008v cy7c018v cy7c009v cy7c019v 3.3 v 64 k/128 k 8/9 dual-port static ram [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 2 of 23 functional description the cy7c008v/009v and cy7c018v/019v are low-power cmos 64 k, 128 k 8/9 dual-port static rams. various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. the devices can be utilized as standalone 8/9-bit dual-port static rams or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static ram. an m/s pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. application areas include interprocessor/multipro cessor designs, communications status buffering, and dual-port video/graphics memory. each port has independent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy signals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) permits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side can control the latch (semaphor e) at any time. control of a semaphore indicates that a shared resource is in use. an automatic power-down feature is controlled independently on each port by a chip select (ce ) pin. the cy7c008v/009v and cy7c018v/019v are available in 100-pin thin quad plastic flatpacks (tqfp). [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 3 of 23 contents pin configurations ........................................................... 4 selection guide ................................................................ 5 pin definitions .................................................................. 6 maximum ratings ............................................................. 6 operating range ............................................................... 6 electrical characteristics ................................................. 7 capacitance ...................................................................... 7 ac test loads and waveforms ....................................... 8 switching characteristics ................................................ 8 data retention mode ...................................................... 10 timing .............................................................................. 10 switching waveforms .................................................... 11 read cycle no.1 (either port address access) ........ 11 read cycle no.2 (either port ce /oe access) .......... 11 read cycle no. 3 (either port) .................................. 11 write cycle no. 1: r/w controlled timing ................ 12 write cycle no. 2: ce controlled timing .................. 12 semaphore read after write timing, either side ..... 13 timing diagram of semaphore contention ............... 13 timing diagram of read with busy (m/s =high) .... 14 write timing with busy input (m/s =low) ................. 14 busy timing diagram no. 1 (ce arbitration) ............. 15 busy timing diagram no. 2 (address arbitration) .... 15 architecture .................................................................... 17 functional description ............ .............. .............. ........... 17 write operation ......................................................... 17 read operation ....... .............. .............. .............. ........ 17 interrupts ................................................................... 17 busy .......................................................................... 17 master/slave ............................................................. 17 semaphore operation ............................................... 17 ordering information ...................................................... 19 128 k 8 3.3 v asynchronous dual-port sram ...... 19 ordering code definitions ..... .................................... 19 package diagram ............................................................ 20 acronyms ........................................................................ 21 document conventions ................................................. 21 units of measure ....................................................... 21 document history page ................................................. 22 sales, solutions, and legal information ...................... 23 worldwide sales and design s upport ......... .............. 23 products .................................................................... 23 psoc solutions ......................................................... 23 [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 4 of 23 pin configurations 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 nc nc a7r a8r a9r a10r a15r a12r a14r gnd nc nc ce 0r a13r a11r nc nc ce1r sem r r/w r oe r gnd gnd nc a16r 58 57 56 55 54 53 52 51 cy7c008v (64 k 8) nc nc a7l a8l a9l a10l a15l a12l a14l vcc nc nc ce 0l a13l a11l nc nc ce1l sem l r/w l oe l gnd nc nc a16l 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 nc nc a6l a5l a4l a3l int l a1l nc gnd m/s a0r a1r a0l a2l busy r int r a2r a3r a4r a5r a6r nc nc busy l 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 nc nc nc i/o7r i/o6r i/o5r i/01r i/o3r i/o2r gnd vcc gnd i/o2l vcc i/o4r i/o0l i/o1l i/o3l i/o4l i/o5l i/o6l i/o7l nc gnd i/o0r 33 32 31 30 29 28 27 26 cy7c009v (128 k 8) figure 1. 100-pin tqfp (top view) [4] [4] note 4. this pin is nc for cy7c008v. [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 5 of 23 selection guide cy7c018v/019v ?15 cy7c018v/019v ?20 cy7c018v/019v ?25 unit maximum access time 15 20 25 ns typical operating current 125 120 115 ma typical standby current for i sb1 (both ports ttl level) 35 35 30 ma typical standby current for i sb3 (both ports cmos level) 10 10 10 ? a 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 nc nc a7r a8r a9r a10r a15r a12r a14r gnd nc nc ce 0r a13r a11r nc nc ce1r sem r r/w r oe r gnd gnd nc a16r 58 57 56 55 54 53 52 51 cy7c018v (64 k 9) nc nc a7l a8l a9l a10l a15l a12l a14l vcc nc nc ce 0l a13l a11l nc nc ce1l sem l r/w l oe l gnd nc nc a16l 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 nc nc a6l a5l a4l a3l busy l a1l int l gnd vcc int r a0r a0l a2l m/s busy r a1r a2r a3r a4r a5r a6r nc gnd 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 nc nc i/o8r i/o7r i/o6r i/o5r i/01r i/o3r i/o2r gnd vcc gnd i/o2l vcc i/o4r i/o0l i/o1l i/o3l i/o4l i/o5l i/o6l i/o7l i/o8l gnd i/o0r 33 32 31 30 29 28 27 26 cy7c019v (128 k 9) figure 2. 100-pin tqfp (top view) [5] [5] note 5. this pin is nc for cy7c018v. [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 6 of 23 maximum ratings [6] exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ................................ ?65 ? c to +150 ? c ambient temperature with power applied ........................................... ?55 ? c to +125 ? c supply voltage to ground potenti al ...............?0.5 v to +4.6 v dc voltage applied to outputs in high z state ......................... ?0.5 v to v cc + 0.5 v dc input voltage .................................. ?0.5 v to v cc + 0.5 v output current into outputs (low) .............................. 20 ma static discharge voltage........... ............................... > 1100 v latch-up current .................................................... > 200 ma pin definitions left port right port description ce 0l , ce 1l ce r , ce 1r chip enable (ce is low when ce 0 ??? v il and ce 1 ? v ih ) r/w l r/w r read/write enable oe l oe r output enable a 0l ?a 16l a 0r ?a 16r address (a 0 ?a 15 for 64 k devices and a 0 ?a 16 for 128 k devices) i/o 0l ?i/o 8l i/o 0r ?i/o 8r data bus input/output (i/o 0 ?i/o 7 for 8 devices and i/o 0 ?i/o 8 for 9) sem l sem r semaphore enable int l int r interrupt flag busy l busy r busy flag m/s master or slave select v cc power gnd ground nc no connect operating range range ambient temperature v cc commercial 0 ? c to +70 ? c 3.3 v 300 mv industrial [7] ?40 ? c to +85 ? c 3.3 v 300 mv notes 6. the voltage on any input or i/o pin cannot exceed the power pin during power-up. 7. industrial parts are available in cy7c009v and cy7c019v only. [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 7 of 23 electrical characteristics over the operating range parameter description cy7c018v/019v unit ?15 ?20 ?25 min typ max min typ max min typ max v oh output high voltage (v cc = min, i oh = ?4.0 ma) 2.4 ? ? 2.4 ? ? 2.4 ? ? v v ol output low voltage (v cc = min, i oh = +4.0 ma) ? 0.4 ? 0.4 ? 0.4 v v ih input high voltage 2.2 ? 2.2 ? 2.2 ? v v il input low voltage ? 0.8 ? 0.8 ? 0.8 v i ix input leakage current ?5 5 ?5 5 ?5 5 ? a i oz output leakage current ?10 10 ?10 10 ?10 10 ? a i cc operating current (v cc = max, i out = 0 ma) outputs disabled commercial ? 125 185 ? 120 175 ? 115 165 ma industrial [8] ? 140 195 ? ma i sb1 standby current (both ports ttl level) ce l and ce r ? v ih , f = f max commercial 35 50 35 45 30 40 ma industrial [8] ?4555?ma i sb2 standby current (one port ttl level) ce l | ce r ? v ih , f = f max commercial 80 120 75 110 65 95 ma industrial [8] ? 85 120 ? ma i sb3 standby current (both ports cmos level) ce l and ce r ? v cc ?? 0.2 v, f = 0 commercial 10 250 10 250 10 250 ? a industrial [8] ? 10 250 ? ? a i sb4 standby current (one port cmos level) ce l | ce r ? v ih , f = f max [9] commercial 75 105 70 95 60 80 ma industrial [8] ? 80 105 ? ma capacitance [10] parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 10 pf c out output capacitance 10 pf notes 8. industrial parts are available in cy7c009v and cy7c019v only. 9. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 . 10. tested initially and after any design or proces s changes that may affect these parameters. [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 8 of 23 ac test loads and waveforms 3.0 v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses (a) normal load (load 1) r1 = 590 ? 3.3 v output r2 = 435 ? c = 30 pf v th = 1.4 v output (b) thvenin equivalent (load 1) (c) three-state delay (load 2) 3.3 v output r th = 250 ? ? ? including scope and jig) (used for t lz , t hz , t hzwe, & t lzwe c = 30 pf c = 5 pf r1 = 590 ? r2 = 435 ? over the operating range [11] parameter description cy7c018v/019v unit ?15 ?20 ?25 min max min max min max read cycle t rc read cycle time 15 ? 20 ? 25 ? ns t aa address to data valid ? 15 ? 20 ? 25 ns t oha output hold from address change 3 ? 3 ? 3 ? ns t ace [12] ce low to data valid ?15?20?25ns t doe oe low to data valid ?10?12?13ns t lzoe [13, 14, 15] oe low to low z 3 ? 3 ? 3 ? ns t hzoe [13, 14, 15] oe high to high z ?10?12?15ns t lzce [13, 14, 15] ce low to low z 3 ? 3 ? 3 ? ns t hzce [13, 14, 15] ce high to high z ? 10 ? 12 ? 15 ns t pu [15] ce low to power-up 0 ? 0 ? 0 ? ns t pd [15] ce high to power-down ? 15 ? 20 ? 25 ns t abe [12] byte enable access time ?15?20?25ns notes 11. test conditions assume signal transition time of 3 ns or less , timing reference levels of 1.5 v, input pulse levels of 0 to 3.0 v, and output loading of the specified i oi /i oh and 30 pf load capacitance. 12. to access ram, ce = l, ub = l, sem = h. to access semaphore, ce = h and sem = l. either condition must be valid for the entire t sce time. 13. at any given temperature and voltag e condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 14. test conditions used are load 2. 15. this parameter is guaranteed by design, but it is not producti on tested.for information on port-to-port delay through ram ce lls from writing port to reading port, refer to read timing with busy waveform. [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 9 of 23 write cycle t wc write cycle time 15 ? 20 ? 25 ? ns t sce [16] ce low to write end 12 ? 16 ? 20 ? ns t aw address valid to write end 12 ? 16 ? 20 ? ns t ha address hold from write end 0 ? 0 ? 0 ? ns t sa [16] address set-up to write start 0 ? 0 ? 0 ? ns t pwe write pulse width 12 ? 17 ? 22 ? ns t sd data set-up to write end 10 ? 12 ? 15 ? ns t hd data hold from write end 0 ? 0 ? 0 ? ns t hzwe [17, 18] r/w low to high z ?10?12?15ns t lzwe [17, 18] r/w high to low z 3 ? 3 ? 3 ? ns t wdd [19] write pulse to data delay ? 30 ? 40 ? 50 ns t ddd [19] write data valid to read data valid ? 25 ? 30 ? 35 ns busy timing [20] t bla busy low from address match ? 15 ? 20 ? 20 ns t bha busy high from address mismatch ? 15 ? 20 ? 20 ns t blc busy low from ce low ?15?20?20ns t bhc busy high from ce high ?15?16?17ns t ps port set-up for priority 5 ? 5 ? 5 ? ns t wb r/w high after busy (slave) 0 ? 0 ? 0 ? ns t wh r/w high after busy high (slave) 13?15?17? ns t bdd [21] busy high to data valid ?15?20?25ns interrupt timing [20] t ins int set time ?15?20?20ns t inr int reset time ?15?20?20ns semaphore timing t sop sem flag update pulse (oe or sem ) 10?10?12? ns t swrd sem flag write to read time 5 ? 5 ? 5 ? ns t sps sem flag contention window 5 ? 5 ? 5 ? ns t saa sem address access time ?15?20?25ns notes 16. to access ram, ce = l, ub = l, sem = h. to access semaphore, ce = h and sem = l. either condition must be valid for the entire t sce time. 17. test conditions used are load 2. 18. this parameter is guaranteed by design, but it is not producti on tested.for information on port-to-port delay through ram ce lls from writing port to reading port, refer to read timing with busy waveform. 19. for information on port-to-port delay through ram cells from writing port to reading port, refer to read timing with busy wa veform. 20. test conditions used are load 1. 21. t bdd is a calculated parameter and is the greater of t wdd ?t pwe (actual) or t ddd ?t sd (actual). switching characteristics over the operating range [11] (continued) parameter description cy7c018v/019v unit ?15 ?20 ?25 min max min max min max [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 10 of 23 data retention mode the cy7c008v/009v and cy7c018v/019v are designed with battery backup in mind. data retention voltage and supply current are guaranteed over temperature. the following rules ensure data retention: 1. chip enable (ce ) must be held high during data retention, within v cc to v cc ? 0.2 v. 2. ce must be kept between v cc ? 0.2 v and 70% of v cc during the power-up and power-down transitions. 3. the ram can begin operation > t rc after v cc reaches the minimum operating voltage (3.0 v). timing parameter test conditions [22] max unit icc dr1 @ vcc dr = 2 v 50 ? a data retention mode 3.0 v 3.0 v v cc ? ? 2.0 v v cc to v cc ? 0.2 v v cc ce t rc v ih note 22. ce = v cc , v in = gnd to v cc , t a = 25 ?? c. this parameter is guaranteed but not tested. [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 11 of 23 switching waveforms notes 23. r/w is high for read cycles. 24. device is continuously selected ce = v il . this waveform cannot be used for semaphore reads. 25. oe = v il . 26. address valid prior to or coincident with ce transition low. 27. to access ram, ce = v il , sem = v ih . to access semaphore, ce = v ih , sem = v il . t rc t aa t oha data valid previous data valid data out address t oha read cycle no.1 (either port address access) [23, 24, 25] t ace t lzoe t doe t hzoe t hzce data valid t lzce t pu t pd i sb i cc data out oe ce current read cycle no.2 (either port ce /oe access) [23, 26, 27] data out t rc address t aa t oha ce t lzce t abe t hzce t ace t lzce read cycle no. 3 (either port) [23, 25, 26, 27] [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 12 of 23 notes 28. r/w must be high during all address transitions. 29. a write occurs during the overlap (t sce or t pwe ) of a low ce or sem . 30. t ha is measured from the earlier of ce or r/w or (sem or r/w ) going high at the end of write cycle. 31. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t pwe . 32. to access ram, ce = v il , sem = v ih . 33. transition is measured ? 500 mv from steady state with a 5 pf load (including scope and jig). this parameter is sampled and not 100% tested. 34. during this period, the i/o pins are in the out put state, and input signals must not be applied. 35. if the ce or sem low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high-impedance state. switching waveforms (continued) t aw t wc t pwe t hd t sd t ha ce r/w oe data out data in address t hzoe t sa t hzwe t lzwe write cycle no. 1: r/w controlled timing [28, 29, 30, 31] [33] [33] [31] [32] note 34 note 34 t aw t wc t sce t hd t sd t ha ce r/w data in address t sa write cycle no. 2: ce controlled timing [28, 29, 30, 35] [32] [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 13 of 23 notes 36. ce = high for the duration of the above timing (both write and read cycle). 37. i/o 0r = i/o 0l = low (request semaphore); ce r = ce l = high. 38. semaphores are reset (available to both ports) at cycle start. 39. if t sps is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpr edictable. switching waveforms (continued) t sop t saa valid adress valid adress t hd data in valid data out valid t oha t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle oe r/w i/o 0 sem a 0 ?a 2 semaphore read after write timing, either side [36] match t sps a 0l ?a 2l match r/w l sem l r/w r sem r timing diagram of semaphore contention [37, 38, 39] a 0r ?a 2r [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 14 of 23 note 40. ce l = ce r = low. switching waveforms (continued) valid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe valid t sd t hd address l t ps t bla t bha t bdd busy l timing diagram of read with busy (m/s =high) [40] t pwe r/w busy t wb t wh write timing with busy input (m/s =low) [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 15 of 23 note 41. if t ps is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side busy will be asserted. switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc address l,r busy r ce l ce r busy l ce r ce l address l,r busy timing diagram no. 1 (ce arbitration) [41] ce l valid first: ce r valid first: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r busy timing diagram no. 2 (address arbitration) [41] right address valid first: left address valid first: [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 16 of 23 notes 42. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 43. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. switching waveforms (continued) write ffff (1ffff for cy7c009v/19v) t wc t ha read ffff t rc t inr write fffe (1ffff for cy7c009v/19v) t wc read 1ffe t inr t rc address r ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r address l r/w l ce l int r t ins t ha t ins (1ffff for cy7c009v/19v) (1ffff for cy7c009v/19v) [42] [43] [43] [43] [42] [43] right side clears int l : right side sets int l : right side clears int r : left side sets int r : interrupt timing diagrams [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 17 of 23 architecture the cy7c008v/009v and cy7c018v /019v consist of an array of 64 k and 128 k words of 8 and 9 bits each of dual-port ram cells, i/o and address lines, and control signals (ce , oe , r/w ). these control pins permit independent access for reads or writes to any location in memory. to handle simultaneous writes/reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be utilized for port-to-port communication. two semaphore (sem ) control pins are used for allocating shared reso urces. with the m/s pin, the devices can function as a master (busy pins are outputs) or as a slave (busy pins are inputs). the devices also have an automatic power-down feature controlled by ce . each port is provided with its own output enable control (oe ), which allows data to be read from the device. functional description write operation data must be set up for a duration of t sd before the rising edge of r/w in order to guarantee a vali d write. a writ e operation is controlled by either the r/w pin (see write cycle no. 1 waveform) or the ce pin (see write cycle no. 2 waveform). required inputs for non-contention operations are summarized in table 1 on page 18 . if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is r ead on the output; otherwise the data read is not deterministic. data will be valid on the port t ddd after the data is presented on the other port. read operation when reading the device, the user must assert both the oe and ce pins. data will be available t ace after ce or t doe after oe is asserted. if the user wishes to access a semaphore flag, then the sem pin must be asserted instead of the ce pin, and oe must also be asserted. interrupts the upper two memory locations may be used for message passing. the highest memory location (ffff for the cy7c008/18, 1ffff for the cy7c00 9/19) is the mailbox for the right port and the second-highest memory location (fffe for the cy7c008/18, 1fffe for the cy7c009/19) is the mailbox for the left port. when one port writes to the other port?s mailbox, an interrupt is generated to the owner. the interrupt is reset when the owner reads the contents of the mailbox. the message is user defined. each port can read the other po rt?s mailbox without resetting the interrupt. the active state of th e busy signal (to a port) prevents the port from setting the interrupt to the winning port. also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. if an application does not require message passing, do not connect the interrupt pin to the processor?s interrupt request input pin. the operation of the interrupts a nd their interaction with busy are summarized in table 2 on page 18 . busy the cy7c008v/009v and cy7c018v/019v provide on-chip arbitration to resolve simultaneous memory location access (contention). if both ports? ce s are asserted and an address match occurs within t ps of each other, the busy logic will determine which port has access. if t ps is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. busy will be asserted t bla after an address match or t blc after ce is taken low. master/slave a m/s pin is provided in order to expand the word width by configuring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this will allow the device to interface to a master device with no external components. writing to slave devices must be delayed until after the busy input has settled (t blc or t bla ), otherwise, the slave chip may begin a write cycle during a contention situation. when tied high, the m/s pin allows the device to be used as a master and, therefore, the busy line is an output. busy can then be used to send the arbitration outcome to a slave. semaphore operation the cy7c008v/009v and cy7c018v/019v provide eight semaphore latches, which are separate from the dual-port memory locations. semaphores are used to reserve resources that are shared between the two ports.the state of the semaphore indicates that a resour ce is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before attempting to read the semaphore. the semaphore value will be available t swrd + t doe after the rising edge of the semaphore write. if the left port was succe ssful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. when the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. if the left side no longer requires the semaphore, a one is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip select for the semaphore latches (ce must remain high during sem low). a 0?2 represents the semaphore address. oe and r/w are used in the same manner as a normal memory access. when writing or reading a semaphore, the other addre ss pins have no effect. when writing to the semaphore, only i/o 0 is used. if a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. that semaphore can now only be modified by the side showing zero (the left port in this case). if the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. however, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. table 3 on page 18 shows sample semaphore operations. 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cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 18 of 23 when reading a semaphore, all data lines output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. table 1. non-contending read/write inputs outputs ce r/w oe sem i/o 0 ? i/o 8 operation h x x h high z deselected: power-down h h l l data out read data in semaphore flag x x h x high z i/o lines disabled h x l data in write into semaphore flag l h l h data out read l l x h data in write l x x l not allowed table 2. interrupt operation example (assumes busy l = busy r = high) [44] left port right port function r/w l ce l oe l a 0l?16l int l r/w r ce r oe r a 0r?16r int r set right int r flag l l x ffff (or 1ffff) x x x x x l [46] reset right int r flag x x x x x x l l ffff (or 1ffff) h [45] set left int l flag x x x x l [45] l l x fffe (or 1fffe) x reset left int l flag x l l fffe (or 1fffe) h [46] x x x x x table 3. semaphore operation example function i/o 0 ? i/o 8 left i/o 0 ? i/o 8 right status no action 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token right port writes 0 to semaphore 0 1 no change. right side has no write access to semaphore left port writes 1 to semaphore 1 0 right port obtains semaphore token left port writes 0 to semaphore 1 0 no change. left port has no write access to semaphore right port writes 1 to semaphore 0 1 left port obtains semaphore token left port writes 1 to semaphore 1 1 semaphore free right port writes 0 to semaphore 1 0 right port has semaphore token right port writes 1 to semaphore 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token left port writes 1 to semaphore 1 1 semaphore free notes 44. a 0l?16l and a 0r?16r , 1ffff/1fffe for the cy7c009v/19v. 45. if busy r = l, then no change. 46. if busy l = l, then no change. [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 19 of 23 ordering information ordering code definitions 128 k 8 3.3 v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 15 cy7c009v-15axc a100 100-pin pb-free thin quad flat pack commercial 20 cy7c009v-20axi a100 100-pin pb-free thin quad flat pack industrial 25 CY7C009V-25AXC a100 100-pin pb-free thin quad flat pack commercial operating range: x = c or i c = commercial; i = industrial pb-free package: a = (a100) 100-pin thin quad flat pack speed bin: xx = 15/20/25 3.3 v part 64 k / 128 k dual port family 00 = 8 technology code: c = cmos marketing code: 7 = sram company id: cy = cypress 7 cy 00 v - xx a c 9 x x [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 20 of 23 package diagram figure 3. 100-pin thin plastic quad flat pack (tqfp) a100 51-85048 *d [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 21 of 23 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor ce chip enable i/o input/output oe output enable sram static random access memory tqfp thin quad flat pack ttl transistor?transistor logic we write enable symbol unit of measure ns nano seconds vvolts a micro amperes ma milli amperes ms milli seconds mv milli volts mhz mega hertz pf pico farad wwatts c degree celcius [+] feedback
cy7c008v/009v cy7c018v/019v document number: 38-06044 rev. *e page 22 of 23 document history page document title: cy7c008v/009 v, cy7c018v/019v 3. 3 v 64 k/128 k 8/9 dual-port static ram document number: 38-06044 rev. ecn no. issue date orig. of change description of change ** 110192 09/29/01 szv change from spec number: 38-00669 to 38-06044 *a 113541 04/15/02 oor change pin 85 from busyl to busyr (pg. 3) *b 122294 12/27/02 rbi power up requirements added to maximum ratings information *c 393440 see ecn yim added pb-free logo added pb-free parts to ordering information: cy7c008v-25axc, cy7c009v-15axc, cy7c009v-20axi, CY7C009V-25AXC, cy7c019v-15axc, cy7c019v-20axc, cy7c019v-20axi, cy7c019v-25axc *d 2896038 03/19/10 rame removed inactive parts from ordering information table updated package diagram *e 3081242 11/09/2010 admu added ordering code definitions . added acronyms and units of measure . minor edits and updated in new template. [+] feedback
document number: 38-06044 rev. *e revised november 9, 2010 page 23 of 23 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c008v/009v cy7c018v/019v ? cypress semiconductor corporation, 2001-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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